| Date | Presenter | Topic | slides+materials |
| 2003 Jun 16 | | Random Walks in a Supply Network(DAC 2003, by Qian et al.) | Slides |
| 2003 Jun 19 | | Two papers in DAC 2003 : Floorplanning and Placement | Slides |
| 2003 Jun 23 | | A paper from DAC 2003 on Parasitic Extraction | Slides |
| 2003 Jun 26 | | About Prescribed Skew Clock Tree (ICCD 2003) | Slides |
| 2003 Jul 3 | | Pushing ASIC Performance in a Power Envelope (DAC 2003, by Puri et al.) | Slides |
| 2003 Jul 7 | | About Wire Shaping Based Skew Variation Analysis | Slides |
| 2003 Jul 10 | | About Non-tree routing (ICCAD 2002, by A.B. Kahng) | Slides |
| 2003 Jul 14 | | About buffered clock tree routing(ISPD 2000, by Aziz's group at UT Austin) | Slides |
| 2003 Jul 17 | | ``A General Probabilistic Framework for worst case timing analysis'' (DAC 2002, by Michael Orshansky and Kurt Keutzer) | Slides |
| 2003 Jul 21 | | Statistical Delay Computation Considering Spatial Correlations (ASPDAC 2003, by Agarwal et al) | Slides |
Note: All materials are for internal access only. Request of the materials should be made to the presenter. | Date | Presenter | Topic | slides+materials |
| 2003 Jan 27 | | An O(nlogn) time algorithm for optimal buffer insertion | Slides |
| 2003 Feb 3 | | UST/DME: A clock tree router for general skew constraints (ICCAD 2000, by Tsao et al.) | Slides |
| 2003 Feb 10 | | Estimating routing congestion using probabilistic analysis (by Lou et al., TCAD 01/2002) | Slides |
| 2003 Feb 17 | | MATCH project by Prith Banerjee's group at Northwestern University | Slides |
| 2003 Mar 3 | | Interval Methods for Modeling Uncertainity in RC Timing Analysis (by Cheryl Harkness and Daniel Lopresti) | Slides |
| 2003 Mar 24 | | Post global routing crosstalk synthesis (TCAD 12/1997, by Xue, T.; Kuh, E.S.; Wang, D.) | Slides |
| 2003 Mar 31 | | Porosity Aware Buffered Steiner Tree Construction | Slides |
| 2003 Apr 7 | | Survey: Simulations of MEMS devices | Slides |
Note: All materials are for internal access only. Request of the materials should be made to the presenter. | Date | Presenter | Topic | slides+materials |
| 2002 Sep 11 | | Buffer Insertion with Adapative Blockage Avoidance | Slides |
| 2002 Sep 18 | | Behavioral Modeling of Analog Circuits by Wavelet Collocation Method | Slides+paper |
| 2002 Sep 25 | | The rectilinear Steiner arborescence problem is NP-complete | Slides |
| 2002 Oct 2 | | Capacitance Extraction | |
| 2002 Oct 9 | | Circuit Clustering with Variable Interconnect Delay | |
| 2002 Oct 16 | | Design of GHz VLSI clock distribution circuit | |
| 2002 Oct 23 | | Topics about New CMOS models | |
| 2002 Oct 30 | | Topics about New Fault Modeling | |
| 2002 Nov 5 | | ``A Fast Algorithm for Context-Aware Buffer Insertion'' by J. Lillis | |
| 2002 Nov 12 | | Some Interesting Problems and Algorithms | |
| 2002 Nov 19 | | Parametric Static Timing Analysis | Slides |
| 2002 Nov 26 | | Moment Computation of Non-tree Circuits | |
Note: All materials are for internal access only. Request of the materials should be made to the presenter. 
ece.tamu.edu)