Logic Design & Testing
Logic Synthesis
Synopsis Research
Synopsis Research FTP
Portland Logic Optimization group
Berkeley CAD software
Berkeley Logic Design FTP site
SIS for DOS
Demain - Decomposer into FPGA
Testing & Diagnostics
PROACTIVE Computer-aided Testing and Verification Research
IGATE Illinois - ATPG Tools, tests for benchmarks
TurboTester
DefGen - ATPG
Atalanta, FSIM, HOPE - ATPG, fault simulators
Benchmarks
CBL - the collection of logic synthesis benchmarks
Description of ISCAS benchmarks
ITC'99 Benchmark Homepage
ITC'99 Benchmarks from POLITO
ITC'02 SOC Benchmarks
Papers
SIGDA Proceeding archives
SIGDA Compendium
Synopsis Research archives
Research Index
Other
TU Liberec
Ondøej Novák
Sybille Hellebrand
Marek Perkowski
Alan Mischenko
Nur A. Touba
R.K. Brayton
H.J. Wunderlich