Bo Hu received a B.S. degree in Electronics Engineering (1999/09) from Tsinghua University, China, and a M.S. degree (2002) and a Ph.D degree (2004/03) in Computer Engineering from University of California, Santa Barbara, USA.
He is working in Velogix Inc. since April, 2004. He worked as graduate student researcher in Electrical and Computer Engineering Department of the University of California at Santa Barbara (1999/09 - 2004/03). He worked as summer intern in Quicklogic Corp. Sunnyvale, CA (June-Sept 2000), Verplex Systems Corp., Milpitas, CA (June-Sept. 2001) and Cadence Berkeley Labs, Berkeley, CA (June-Sept. 2002). His research interests include deep sub-micron physical design and logic synthesis.
It is well known that direct application of non-constrained quadratic programming in the placement results in excessive cell overlapping. To solve this problem, we propose to introduce fixed points into non-constrained quadratic-programming formulation. Fixed points act as fixed pseudo cells and can be used to pull cells out of a dense region such that the overlapping is reduced. We develop an efficient multi-level placer based on fixed-point technique. The new placer has a novel property of individual wire length predictability. We demonstrate that it is capable of predicting more than half of the interconnects at a very early stage of the whole placement process while still achieves competitive total wire length result comparing to existing state-of-art placers.
FPI: Fast Placer Implementation
This research addresses the problem of improving efficiency of placement algorithms. We employ a fine granularity clustering technique to reduce the placement problem size. The reduction is feasible because a global placer may not need to operate on the bottom-level netlist in order to achieve a competitive result. We propose two new clustering algorithms. One applies net absorption, and the other is based on wire-length prediction. We have integrated those algorithms into our Fast Placer Implementation(FPI) framework. We demonstrate that FPI achieves significant speedup while maintaining good placement quality.
ExtremeTime: Timing Driven Placement
MPM: Multi-objective Placement Migration
We present an incremental placement approach to optimize simultaneously a circuit's routability, performance and power.
B. Hu, and M. Marek-Sadowska, "Multi-level VLSI Placement with Inherent Interconnect Predictability", submitted to IEEE Trans. on CAD
B. Hu, and M. Marek-Sadowska, "Multi-objective Placement Migration for Deep Sub-micron VLSI designs", submitted to IEEE Trans. on CAD
C-W. Chang, M.-F Hsiao, B. Hu, K. Wang, M. Marek-Sadowska, C.-K Cheng, S.-Jie Chen, "Fast Post-Placement Optimization Using Functional Symmetries. IEEE Trans. CAD, January, 2004.
B. Hu and M. Marek-Sadowska, "Fine Granularity Clustering based Placement", IEEE Trans. on CAD. April, 2004
Conference Paper
B. Hu, Y. Watanabe, A. Kondratyev and M. Marek-Sadowska, "Gain-based technology mapping for discrete-size cell libraries", Proc. ACM/IEEE Design Automation Conference, June 2003. Best Paper Candidate.
Q.H. Liu, B. Hu, and M. Marek-Sadowska, "Wire Length Prediction in Constraint driven Placement", Proc. Intl. Symp. on System Level Interconnect Prediction,2003.
B. Hu and Marek-Sadowska, "Wire length prediction based clustering and its application in placement", Proc. ACM/IEEE Design automation conference, June 2003.
B. Hu, H. Jiang, Q. Liu, and M. Marek-Sadowska, "Synthesis and Placement Flow for Gain-based Programmable Regular Fabrics", Proc. Intl. Symp. On Physical Design, 2003.
B. Hu and M. Marek-Sadowska, "Fine granularity clustering for large-scale placement problems", Proc. Intl. Symp. on physical design. 2003.
B. Hu and M. Marek-Sadowska, "Congestion Minimization during Placement without Estimation", Proc. Intl. Conf. Computer-Aided Design, 2002.
Bo Hu, and M. Marek-Sadowska, "FAR: Fixed-points and Relaxation based Placement", Proc. Intl. Symp. on Physical Design, San Diego, 2002.
C.-W Chang, B. Hu and M. Marek-Sadowska, "In-place delay constrained power optimization using functional symmetries", Proc. Design Automation and Test in Europe, 2001.