Graduate Students

Graduate Students (last update: October 2006)

³Õ¤h¥Í Ph.D. Students
1. ³¯®õã¸ Tai-Chen Chen (2001-present, Graduate Institute of Electronics Engineering, NTU)
  Dissertation directions: Gridless routing considering nanometer electrical effects
2. ¤è¦tºú Athena Yu-Luen Fang (2003-present, Graduate Institute of Electronics Engineering, NTU)
  Dissertation directions: Floorplanning
3. ³ëªÃÂE (2003-present, Graduate Institute of Computer Science and Information Engineering, NTU; co-supervised with Prof. Chia-Lin Yang)
  Dissertation directions: Floorplanning/placement for emerging technologies (reconfigurable systems, bio-chips, etc)
4. ³¯ªF³Ç Tung-Chieh Chen (2004-present, Graduate Institute of Electronics Engineering, NTU)
  Dissertation directions: Floorplanning and placement for large-scale circuits
5. ¦¿õºû Zhe-Wei Jiang (2004-present, Graduate Institute of Electronics Engineering, NTU)
  Dissertation directions: Large-scale mixed-size placement and reliability
6. §õ°ûµÓ Wan-Ping Li (2004-present, Graduate Institute of Electronics Engineering, NTU)
  Dissertation directions: Low-power design methodology for multiple supply/threshold voltages
7. ¹ù¥ú¸U Guang-Wan Liao (2004-present, Graduate Institute of Electronics Engineering, NTU)
  Dissertation directions: Design for manufacturing
8. ¤è®a°¶ Jai-Wei Fang (2005-present, Graduate Institute of Electronics Engineering, NTU)
  Dissertation directions: Routing for flip chips and PCB's
9. ³¯¬Ó¦t Huan-Yu Chen (2005-present, Graduate Institute of Electronics Engineering, NTU)
  Dissertation directions: Manufacturing-aware Routing for large-scale circuits
10. ªL¨Ì¼ä I-Jye Lin (2005-present, Graduate Institute of Electrical Engineering, NTU)
  Dissertation directions: Statistical design optimization and design for manufacturing
11. ªL¬f§» Mark Lin (2005-present, Graduate Institute of Electronics Engineering, NTU)
  Dissertation directions: Analog layout designs
12. ³\´Ü¶¯ Chin-Hsiung Hsu (2006-present, Graduate Institute of Electronics Engineering, NTU)
ºÓ¤h¥Í M.S. Students
1. ªL©¾½n Chung-Wei Lin (2005-present, Graduate Institute of Electronics Engineering, NTU)
  Dissertation directions: Stenier-tree optimization with obstacles
2. ©P«äºÍ Szu-Jui Chou (2005-present, Graduate Institute of Electronics Engineering, NTU)
  Dissertation directions: CMP-aware routing
3. ¼B§»¼Ý Hung-Yi Liu (2005-present, Graduate Institute of Electronics Engineering, NTU)
  Dissertation directions: Power and timing optimization for multiple supply voltages
4. ³¯«H¦¨ Hsin-Chen Chen (2005-present, Graduate Institute of Electrical Engineering, NTU)
  Dissertation directions: Macro placement for large-scale mixed-size circuits
5. §õ©_®p Chi-Fang Lee (2005-present, Graduate Institute of Computer Science and Information Engineering, NTU; co-supervised with Prof. Chia-Lin Yang)
  Dissertation directions: Leakage power optimization
6. ¶À¤hÛ (2006-present, Graduate Institute of Electronics Engineering, NTU)
7. §õ©s²» (2006-present, Graduate Institute of Electronics Engineering, NTU)
8. ²ø©öÀM (2006-present, Graduate Institute of Electronics Engineering, NTU)
9. ³\³ÍµX (2006-present, Graduate Institute of Electrical Engineering, NTU)
10. ³¯«ä¦ö (2007-present, Graduate Institute of Electronics Engineering, NTU)
11. ®}©s·¢ (2007-present, Graduate Institute of Electronics Engineering, NTU)
12. ¾G¥ò¶v (2007-present, Graduate Institute of Electronics Engineering, NTU)
13. °ª·sºú (2007-present, Graduate Institute of Electrical Engineering, NTU)
ºÓ¤h¦bÂ¾¥Í On-Job M.S. Students
1. §õ¶®µ× Jocelyn Lee (2004-present, Graduate Institute of Electronics Engineering, NTU)
2. ¯ÎµY©g Lannie Weng (2005-present, Graduate Institute of Electronics Engineering, NTU)
3. ¤ý¦³¦¨ Yu-Chen Louis Wang (2005-present, Graduate Institute of Electronics Engineering, NTU)
4. ªô³ÓÂ× Sheng-Feng Sam Chiu (2006-present, Graduate Institute of Electronics Engineering, NTU)
5. ´ö§Ó½å Nail Tang (2006-present, Graduate Institute of Electrical Engineering, NTU)
²¦·~®Õ¤Í Alumni/Alumnae
- ³Õ¤h Ph.D.
  1. §d¥ú¶{ Guang-Ming Wu (1997-2000, Dept. of Computer & Information Science, NCTU)
    Dissertation: Architectures and CAD algorithms for dynamically reconfigurable FPGAs
  2. ªL®a¥Á Jai-Ming Lin (1998-2002, Dept. of Computer & Information Science, NCTU)
    Dissertation: Transitive closure graph representation for general floorplans
  3. ¦¿¿·¦p Hui-Ru Jiang (1998-2002, Dept. of Electronics Engineering, NCTU, co-supervised with Prof. Jing-Yang Jou)
    Dissertation: Interconnect optimization for deep-submicron technologies
  4. ¦ó©v©ö Chung-Yi Ho (2001-2005, Graduate Institute of Electrical Engineering, NTU, co-supervised with Prof. Sao-Jie Chen)
    Dissertation: mSIGMA: A multilevel full-chip routing system considering SIGnal-integrity and MAnufacturability
- ºÓ¤h M.S.
  1. ±i¸ÎªF Yu-Dong Chang (1996-1998, Dept. of Computer and Information Science, NCTU)
    Thesis title: Design and Analysis of Universal Switch Blocks for Hierarchical FPGAs
  2. ªL®a¥Á Jai-Ming Lin (1997-1998, Dept. of Computer and Information Science, NCTU)
    Thesis title: Matching-Based Algorithms for FPGA Segmentation Design
  3. ¤ý¦¨Þ± Cherng-Shiuan Wang (1997-1999, Dept. of Computer and Information Science, NCTU)
    Thesis title: Implementation of a Timing-driven router for FPGAs
  4. ®}°êµ{ Michael Shyu (1997-1999, Dept. of Computer and Information Science, NCTU)
    Thesis title: Generic Universal Switch Blocks
  5. ±i¨|»a Yu-Tsang Chang (1997-1999, Dept. of Computer and Information Science, NCTU)
    Thesis title: Architecture-driven Simultaneous Placement and Global-routing for FPGAs
  6. Á§¤åµq Wen-Hao Shiue (1997-1999, Dept. of Computer and Information Science, NCTU)
    Thesis title: Sequence-pair Based Floorplanning
  7. ÁÂ©s®Ù Meng-Huang Shieh (1997-1999, Dept. of Computer and Information Science, NCTU)
    Thesis title: Crosstalk Minimization for Gridless Channel Routing
  8. ±i¶³´¼ Yun-Chih Chang (1998-2000, Dept. of Computer and Information Science, NCTU)
    Thesis title: B*-trees: A new representation for non-slicing floorplans
  9. ¼ï¹|ºÍ Song-Ra Pan (1998-2000, Dept. of Computer and Information Science, NCTU)
    Thesis title: interconnect optimization for deep submicron
  10. »¯®a¦õ Chia-Tsao Chao (1998-2000, Dept. of Computer and Information Science, NCTU)
    Thesis title: A probability-based approach partitioning algorithm for time-multiplexed FPGAs
  11. ±i®a·½ Chia-Yuan Chang (1998-2000, Dept. of Computer and Information Science, NCTU)
    Thesis title: Formulae for performance optimization with applications to interconnect-driven floorplanning
  12. ¦çÃh®¦ Huai-En Yi (1999-2001, Dept. of Computer and Information Science, NCTU)
    Thesis title: Placement with the boundary constraint using B*-tree
  13. ³¯®õã¸ Tai-Chen Chen (1999-2001, Dept. of Computer and Information Science, NCTU)
    Thesis title: Performance-driven modeling and optimization under the transmission-line delay model
  14. §õ°V¬F Shun-Cheng Li (1999-2001, Dept. of Computer and Information Science, NCTU)
    Thesis title: Multilevel large-scale module floorplanning/placement
  15. §õ²Q±Ó Shu-Min Li (1999-2001, Dept. of Computer and Information Science, NCTU)
    Thesis title: Noise-aware buffer-block planning for interconnect-driven floorplanning
  16. Ò\©|Þ³ Shang-Wei Tu (2000-2001; Dept. of Electronics Engineering, NCTU, co-supervised with Prof. and Dean Wen-Zen Shen)
    Thesis title: On-chip inductance modeling for the coplanar structure
  17. §d¯À½n Shu-Wei Wu (ºÓ¤h±M¯Z, 1999-2002, NCTU)
    Thesis title: Fast power/ground distribution network synthesis for signal integrity-driven floorplanning
  18. ³¯«H¶© Hsin-Lung Chen (2000-2002, Dept. of Computer and Information Science, NCTU)
    Thesis title: Temporal floorplanning using 3D-subTCG
  19. µ{¯q½÷ Yi-Hui Cheng (2000-2002, Dept. of Computer and Information Science, NCTU)
    Thesis title: Integrating buffer planning with floorplanning for simultaneous area, timing, noise, and congestion optimization
  20. ªL¥@¥ Shih-Ping Lin (2000-2002, Dept. of Computer and Information Science, NCTU)
    Thesis title: A novel framework for multilevel routing considering routability and performance
  21. §d©s¿² Mong-Jang Wu (2001-2003, NCTU)
    Thesis title: Placement with an optimal evaluation scheme for alignment and performance constraints
  22. ¤ý¸tÀs Sheng-Long Wang (2001-2003, Graduate Institute of Electronics Engineering, NTU)
    Thesis title: Accurate delay modeling for buffered RLY/RLC trees
  23. ´^§Ó¬v Chih-Yang Peng (2001-2003, Graduate Institute of Electronics Engineering, NTU)
    Thesis title: Block and input/output buffer placement in flip-chip design
  24. ·¨¤h½å Shih-Shyan Yang (2001-2003, Graduate Institute of Electronics Engineering, NTU)
    Thesis title: Simultaneous floorplanning and power/ground network synthesis
  25. ªL©y°¶ Yi-Wei Lin (2002-2004, Graduate Institute of Electronics Engineering, NTU)
    Thesis title: Thermal-driven Interconnect Optimization by Simultaneous Gate and Wire Sizing
  26. ªL®e¥¿ Jung-Cheng Lin (2002-2004, Graduate Institute of Electronics Engineering, NTU)
    Thesis title: Floorplan and Power/Ground Network Co-synthesis
  27. ³¯¸t¤¥ Sheng-Fong Chen (2002-2004, Graduate Institute of Electronics Engineering, NTU)
    Thesis title: Performance-Driven Routing-Tree Construction with Obstacle Consideration
  28. »¯¤å¼ý Wen-Chang Chao (2002-2004, Graduate Institute of Electronics Engineering, NTU)
    Thesis title: Performance-Driven Block and Input/Output Buffer Placement in Flip-Chip Design
  29. ¿à«T¿o Chung-Ying Lai (2002-2004, Graduate Institute of Communication Engineering, NTU; co-supervised with Prof. Shyh-Kang Jeng)
    Thesis title: Surface Integral Inductance Extraction for General Interconnect Structures
  30. ¤è®a°¶ Jai-Wei Fang (2003-2005, Graduate Institute of Electronics Engineering, NTU)
    Thesis title: An RDL Routing System for Flip-Chip Design
  31. ¼B®¶°¶ Cheng-Wei Liu (2003-2005, Graduate Institute of Electronics Engineering, NTU)
    Thesis title: Floorplan and Power/Ground Network Co-Synthesis for Fast Design Convergence
  32. §d«Û½n (2003-2005, Graduate Institute of Computer Science and Information Engineering, NTU; co-supervised with Prof. Chia-Lin Yang)
    Thesis title: XRoute: A Novel X-Architecture Multilevel Full-Chip Router
  33. ±i®f®p Chen-Feng Chang (2003-2006, Double major; also in Education, Graduate Institute of Electrical Engineering, NTU)
    Thesis title: XRoute: An X-Architecture Full-Chip Router Based on a Novel Multilevel Framework
  34. ½±±öªÚ (2004-2006, Graduate Institute of Electrical Engineering, NTU)
    Thesis title: Post-layout Double-via Insertion for Yield Enhancement
  35. ªL»Aíõ (2004-2006, Graduate Institute of Electrical Engineering, NTU)
    Thesis title: Statistical Timing- and Thermal-driven Circuit Optimization
  36. ³\¤Ñ¹ü (2004-2006, Graduate Institute of Electronics Engineering, NTU)
    Thesis title: A Detailed placement Algorithm for Large-scale VLSI Circuits
  37. ³¯«Û»« (2004-2006, Graduate Institute of Electrical Engineering, NTU)
    Thesis Title: ECO Timing Optimization Using Spare Cells and Technology Remapping