Welcome to Michael Romesis's Home Page

New Contact

• I graduated from UCLA in March 2005. Currently, I work for Magma Design Automation in the Netherlands.
• E-mail: michalis@magma-da.com

Publications

• Koziris N., Romesis M., Tsanakas P., and Papakonstantinou P. An Efficient Algorithm for the Physical Mapping of Clustered Task Graphs onto Multiprocessor Architectures, Proceedings of the 8th Euromicro Workshop on Parallel and Distributed Processing, pp. 406-413, Rhodes, Greece, 2000.
• Cong J., and Romesis M. Performance-Driven Multi-Level Clustering with Application to Hierarchical FPGA Mapping, Proceedings of the Design Automation Conference, pp. 389-394, Las Vegas, NV, 2001. (Related UCLA Technical Report).
• Cong J., Romesis M., and Xie M. Optimality, Scalability and Stability Study of Partitioning and Placement Algorithms, Proceedings of the International Symposium on Physical Design, pp. 88 - 94, Monterey, CA, 2003.
• Cong J., Jagannathan A., Reinman G., and Romesis M. Microarchitecture Evaluation with Physical Planning, Proceedings of the Design Automation Conference, pp. 32 - 35, Anaheim, CA, 2003 (Related UCLA Technical Report).
• Cong J., Romesis M., and Xie M. Optimality and Stability Study of Timing-Driven Placement Algorithms, Proceedings of the International Conference on Computer-Aided Design, pp. 472 - 478, San Jose, CA, 2003 (Related UCLA technical Report).
• Chang C., Cong J., Romesis M., and Xie M. Optimality and Scalability Study of Existing Placement Algorithms, IEEE Transactions on Computer-Aided Design, pp. 537 - 549, April, 2004.
• Cong J., Nataniele G., Romesis M., and Shinnerl J. An Area-Optimality Study of Floorplanning, Proceedings of the International Symposium on Physical Design, pp. 78 - 83, Phoenix, AZ, 2004.
• Cong J., Romesis M., and Shinnerl J. Fast Floorplanning by Look-Ahead Enabled Recursive Bipartitioning, Proceedings of the Asia-South Pacific Design Automation Conference, pp. 1119 - 1122, Shangahi, China, 2005. (Related UCLA technical Report).
• Jagannathan A., Yang H., Konigsfeld K., Milliron D., Mohan M., Romesis M., Reinman G., and Cong J. Microarchitecture Evaluation with Floorplanning and Interconnect Pipelining, Proceedings of the Asia-South Pacific Design Auto mation Conference, pp. 8 - 15, Shangahi, China, 2005.
• Chan T., Cong J., Romesis M. ,Shinnerl J., Sze K., and Xie M. mPL6: A Robust Multi-Level Mixed-Size Placement Engine, Proceedings of the International Symposium on Physical Design, pp. 227 - 229, San Francisco, CA, 2005.
• Cong J., Romesis M., and Shinnerl J. Robust Mixed-Size Placement Under Tight Whitespace Constraints, Proceedings of the International Conference on Computer-Aided Design, pp. 165 - 172, San Jose, CA, 2005.
• Cong J., Romesis M., and Shinnerl J. Fast Floorplanning by Lookahead Enabled Recursive Bipartitioning, to appear in IEEE Transactions on Computer-Aided Design.

Ph.D Dissertation