Prof. Cong in the News

FPGA JOURNAL : A Perfect DSP Storm -- BDTi + High Level Synthesis +FPGA (Jan 2010)
AutoESL was spun out of the prolific UCLA program of Prof. Jason Cong - long time FPGA advocate and expert. AutoESL's AutoPilot takes C, C++, and SystemC as inputs. AutoPilot uses the popular and capable LLVM (low-level virtual machine) compiler, so adding new high-level languages should be a comparatively simple matter. The high-level synthesis "guts" are de-coupled from the language front-end somewhat, so the scheduling and allocation magic can be more or less language independent. In this phase of high-level synthesis adoption where input language is still a question mark, that's a good strategy.

http://www.fpgajournal.com/fpgajournal/feature_articles/20100119-storm/

UCLA Newsroom : NSF awards UCLA $10 million to create customized computing technology (Aug 2009)
The UCLA Henry Samueli School of Engineering and Applied Science has been awarded a $10 million grant by the National Science Foundation's Expeditions in Computing program to develop high-performance, energy efficient, customizable computing that could revolutionize the way computers are used in health care and other important applications. Professor Jason Cong will be the Director of the new UCLA Center for Domain-Specific Computing (CDSC), which will oversee the research.Research being conducted by the CDSC is a collaborative effort among faculty from UCLA's engineering school, medical school and applied mathematics program, as well as faculty from Rice University, Ohio State University and UC Santa Barbara. In particular, Professors Jens Palsberg, Miodrag Potkonjak and Glenn Reinman from the UCLA CS Dept will also be involved in the Center. Congratulations to Professor Cong and all the faculty involved in the center.

http://newsroom.ucla.edu/portal/ucla/ucla-engineering-awarded-10-million-97818.aspx

EE Times : Future of chip design revealed at ISPD (May 2008)
Another paper of note, according to ISPD general chair David Pan, an EE Professor at the University of Texas (Austin), was one showing how to create ultra-high-speed on-chip interconnects using radio frequency (RF) transmission lines. This was presented by Professors Frank Chang and Jason Cong of the University of California at Los Angeles (UCLA). In this interconnect scheme, data is transmitted by modulating an electromagnetic wave along an RF transmission line that can be implemented using standard CMOS processing steps.

http://www.eetimes.com/news/design/showArticle.jhtml?articleID=207400313

SCDsource : Multi-band RF interconnect speeds network-on-chip (Jan 2008)
Researchers at the University of California at Los Angeles (UCLA) have developed a multi-band RF interconnect technology that boosts communications speeds and reduces latency in multicore ICs. The technology will "open a new wave in on-chip communications," says Jason Cong, chairman of UCLA's computer science department.

http://www.scdsource.com/academic.php?id=77

UCLA Newsroom : UCLA scientists working to create smaller, faster integrated circuits (Dec 2007)
Integrated circuits are the "brain" in computers, cell phones, DVD players, iPhones, personal digital assistants, automobiles' navigation systems and anti-lock brakes, and many other electronic devices. A team of UCLA scientists has now demonstrated substantial improvements in integrated circuits, achieved not by costly improvements in manufacturing but by improved computer-aided design software based on better mathematical algorithms.

http://www.newsroom.ucla.edu/portal/ucla/ucla-scientists-make-major-advance-41151.aspx

SolidState Technology : Moore's Law to head z-ward? (Nov 2007)
While the industry struggles to continue on the Moore's Law track, 3D approaches superior to those of systems-on-chip may provide an interim solution if the shrink slows down. A SEMATECH-organized workshop in Albany, NY earlier this month (Oct. 11-12) addressed fundamental issues about 3D, including four reasons why every chipmaker has 3D/TSV approaches on its roadmap, and what needs to be solved before 3D can be effective beyond simple memory.

http://sst.pennnet.com/display_article/310451/5/ARTCL/none/none/1/Moore's-Law-to-head-z-ward?/

EE TIMES : Plain-vanilla EDA gets its due (Sep 2006)
These days, the excitement in EDA centers on electronic system-level tools and design-for-manufacturability. But usnsolved problems remain in plain-vanilla synthesis, placement and routing.

http://www.eetimes.com/showArticle.jhtml?articleID=188500070

EE TIMES : Optimization techniques rein in IC POWER FLOW (May 2006)
In the effort to save power consumption, chip designers increasingly are turning to such techniques as power gating--which requires behavioral simulation and intelligent placement of power-gating transistors--as well as voltage reduction, frequency scaling and limiting accesses to off-chip memory.

http://www.eetimes.com/news/design/showArticle.jhtml?articleID=187201880

FPGA JOURNAL : Blaming the Button -- Physical Synthesis Moves to Mainstream (April 2006)
According to a recent paper published by Jason Cong and Kirill Minkovich of UCLA, the optimality of logic design alone can be off by as much as 70-500X. That's not a percent sign, boys and girls; that big X means that your design may be taking up 70 to 500 times as many LUTs as the best possible solution. The UCLA study compared synthesis results from academic and commercial synthesis tools with known-optimal solutions for a variety of circuits. The paper says that the synthesis tools were 70 times larger in area on average than the known optimal solutions in the test study.

http://www.fpgajournal.com/articles_2006/20060425_button.htm

EE TIMES : Huge FPGA synthesis gap seen -- Circuits may be 70x larger than optimal (February 2006)
Anyone who thinks FPGA synthesis is a solved problem will get a rude awakening at the FPGA 2006 conference here this week. That's when an eminent CAD researcher will show that current synthesis tools may produce circuits that are 70 to 500 times larger than the known optimal solutions in synthetic benchmarks.

http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=180204087

World Journal Daily About Prof. Cong's Talk in PUAASC 2005 Annual Convention : Design Our Career, or Can We? -- Reflection from an Engineering Professor

http://www.worldjournal.com/wj-la-news.php?nt_seq_id=1237232

FPGA JOURNAL : Power -- Suddenly, We Care (April 2005)
For years it was like a slogan. "FPGAs are nice, but they're power hogs." If a new FPGA family offered a 50% performance increase or doubled the LUT count over the previous generation, damn the heatsinks and full-speed ahead. Designers rolled FPGAs in with reckless abandon. Today, however, forces are conspiring to bring power concerns off of the back burner and into the forefront of FPGA design consideration.

http://www.fpgajournal.com/articles_2005/20050426_power.htm

EE TIMES : IC floor planning moves ahead (January 2005)
A new approach to IC floorplanning developed by UCLA researchers is said to reduce wire length while running orders of magnitude faster than previous solutions. The approach was disclosed at the recent ASP-DAC conference in Shanghai.

http://www.eetimes.com/showArticle.jhtml?articleID=59100114

FPGA JOURNAL : Training Tomorrow's Talent (August 2004)
Professor Jason Cong is profiled in the latest issue of FPGA and Programmable Logic Journal. Cong, who is described as a "modern-day luminary" and "master educator," has trained some of the best technical talent in the FPGA design tools industry today.

http://www.fpgajournal.com/index.php?cID=1052

EE TIMES : Power, crosstalk crisis to reroute IC design flows (April 2004)
Power and signal-integrity problems are approaching critical mass and will soon force changes in the nanometer IC design flow. But CAD methodology experts speaking at the Electronic Design Processes 2004 workshop said that the industry is on the case.

http://www.eetimes.com/article/showArticle.jhtml?articleId=19400044&sub_taxonomyID=4217

EE TIMES : FPGA placement performs poorly, study says (November 2003)
Timing-driven placement algorithms for FPGAs can be as much as 50 percent away from optimal results, according to a paper given at the 2003 International Conference on Computer-Aided Design (ICCAD).

http://www.eedesign.com/story/OEG20031113S0048

EE TIMES : Magma acquisition targets structured ASIC market (June 2003)
Making a bold entry into a marketplace barely touched by the big EDA vendors, Magma Design Automation confirmed that it has purchased Los Angeles-based PLD synthesis company Aplus Design Technologies to enter the emerging structured ASIC market.

http://www.eedesign.com/showArticle.jhtml?articleID=17408431

EE TIMES : IC placement benchmarks needed, researchers say (April 2003)
Following up on a controversial study that claimed IC placement algorithms are severely deficient, researchers at the International Symposium on Physical Design (ISPD) struggled to find a benchmarking methodology for IC physical design.

http://www.eedesign.com/showArticle.jhtml?articleID=17408299

EE TIMES : ISPD to present call for EDA benchmarking (April 2003)
A call for open benchmarking of IC placement tools will be among the topics at the 2003 International Symposium on Physical Design (ISPD). ISPD will also review the latest research in topics such as physical synthesis, timing, partitioning, power grid design, lithography, routing, and circuit fabrics.

http://www.eedesign.com/showArticle.jhtml?articleID=17408310

EE TIMES : Placement tools criticized for hampering IC designs (February 2003)
Current IC placement algorithms leave so much excess wire that chip designs are essentially several technology generations behind where they could be, according to a recent paper by researchers at the University of California at Los Angeles (UCLA).

http://www.eedesign.com/showArticle.jhtml?articleID=17408185

EE TIMES : FPGA synthesis tools lose battle with John Henry (February 2000)
In American folklore, John Henry represents man's struggle against obsolescence. Legend has it that John Henry and his sledgehammer beat a steam-powered drill in a tunnel-digging contest, but his heart burst in the effort. An evening panel at FPGA 2000 entitled "The John Henry Syndrome" recast that legend in the FPGA world, asking whether software tools can ever outpace human intervention.

http://www.eetimes.com/article/showArticle.jhtml?articleId=18303632

EE TIMES : Startup rethinks FPGA synthesis (February 2000)
An EDA startup with close ties to the University of California at Los Angeles (UCLA) is quietly preparing next-generation synthesis for large, high-performance PLDs. The startup, Aplus Design Technologies (ADT), came to light at the FPGA 2000 Conference in Monterey with the announcement of a partnership with Cypress Semiconductor Inc.

http://www.eedesign.com/showArticle.jhtml?articleID=17405549

EE TIMES : Panel debates synthesis-layout integration (April 1999)
The difficult issue of whether, and how, to integrate logical and physical design surfaced anew at the International Symposium on Physical Design (ISPD-99), where EDA vendors and academic professors joined a sometimes contentious panel on "layout-driven synthesis or synthesis-driven layout."

http://www.eetimes.com/article/showArticle.jhtml?articleId=18301566&sub_taxonomyID=4217

EE TIMES : ICCAD probes tools for billion-transistor designs (November 1998)
Architectural and physical design must be brought closer together to handle billion-transistor designs, according to panelists at this week's International Conference on Computer-Aided Design (ICCAD 98). The Semiconductor Industry Association's National Technology Roadmap predicts billion-transistor chips by 2010.