LOGIC SYNTHESIS OF DIGITAL SYSTEMS
Professor Jason Cong
4731J Boelter Hall, cong@cs.ucla.edu
Course Description
The aim of this course is to present automatic logic synthesis techniques for computer-aided design (CAD) of very large-scale integrated (VLSI) circuits and systems.
This course will broadly survey the state of the art, and give a detailed study of various problems, pertaining to the logic-level synthesis of VLSI circuits and systems, including: two-level Boolean network optimization, multi-level Boolean network optimization, technology mapping for library-based designs and field-programmable gate-array (FPGA) designs, and state-assignment and re-timing for sequential circuits. The course will also cover various representations of Boolean functions, such as binary decision diagrams (BDDs), and discuss their applications in logic synthesis.
Prerequisites
- CS 51A and CS180 are required or consent of instructor.
Requirements
- 30% homework
- 30% midterm
- 40% presentation and term paper.
Textbooks
- Brayton, Hachtel, McMullen, and Sangiovanni-Vincentelli, "Logic Minimization Algorithms for VLSI Synthesis", Kluwer Academic Publishers, 1984.
- Giovanni De Micheli, "Synthesis and Optimization of Digital Circuits", McGraw-Hill, Inc., 1994.
- Selected research papers from the literature (Proc. of ACM/IEEE Design Automation Conference, Proc. IEEE Intl. Conf. on Computer-Aided Design, IEEE Trans. on CAD, and IEEE Trans on Computers).