People of the VLSI CAD Lab
Current Projects
System Level Design Automation
Logic and Physical Level Design Automation
Design Automation for Emerging Technologies
Past Projects
- Synthesis and Optimization Under Physical Hierarchy. Sponsored by SRC.
- Interconnect-Centric Design Flow and Methodologies. Sponsored by MARCO/GSRC, SRC, NSF, Intel.
- Interconnect Design and Optimization for High-Performance Mixed-Signal MCM Layout. Sponsored by Defense Advanced Research Project Agency (DARPA), Electronic Technology Office (ETO).
- Advanced VLSI CAD Algorithms. Sponsored by NSF Young Investigator Award.
- Computer-Aided Design of High Performance Wireless Networked Systems. Sponsored by ARPA/CSTO.
- The Distributed Supercomputer Supernet -- A Multi-Service Optical Intelligent Network. Sponsored by ARPA/CSTO.
- Interconnect-Driven Layout Synthesis for Performance and Power Optimization. Sponsored by Intel Corp.
- Logic Synthesis and Technology Mapping for FPGAs. Sponsored by Xilinx, AT&T Bell Lab. and California MICRO Program.
- Performance and Power Optimization in VLSI Layout. Sponsored by Fujitsu Laboratories Ltd.
- Rapid System Prototyping Using FPGA Technology. Sponsored by Xerox Foundation.
- Clustering and Partitioning for Very Large-Scale Netlists. Sponsored by Hewlett-Packard under California MICRO Program.
Publications
Software Release
- MPL - A Multilevel Global Placement Tool
- mGP - A Multilevel Global Placement Tool
- IPEM - Performance Estimation Models for Optimized Interconnects
- RASP - FPGA/CPLD Technology Mapping Package
- TRIO - Tree, Repeater and Interconnect Optimization Package
- V4R - Multilayer MCM Router
- MCAS - Multi-Cycle Architectural Synthesis System
- fpgaEva - A Heterogeneous FPGA Evaluation Tool
- Patoma - A Fast Floorplanner by Look-Ahead Enabled Recursive Bipartitioning
- SPCD - Simultaneous Placement with Clustering and Duplication for FPGAs
- xPilot - A Platform-Based Behavioral Synthesis System
Links
Lab News
