*** Defining the placement outline ***

  The directions below are given for Capo (MetaPlacer
  binaries) because some features of Parquet are only
  available through Capo. MetaPlacer accepts input in several
  formats, including input files given to Parquet, and
  automatically determines which format is given (use the
  same option -f).

  When Capo is run on a floorplanning problem, e.g.
      {design.blocks design.nets design.pl}
  Capo automatically constructs a placement outline based on
  the total cell area and the desired whitespace of the
  floorplanning problem.

  The -AR option can be used to shape the placement outline
  to your desired width/height.
  Use the -maxWS option to set the desired % WS.

  (In all cases the outline is aligned to 0,0).

  e.g.
        MetaPlacerTest0.exe -f design -AR 0.14 -maxWS 40 -plotNodes plot -save

  "-f design" refers to input files with base file name "design".
  The "-plotNodes plot" option saves a placement plot,
   in plot.plt (base file name can be changed).
  Alternatively the -plotNodesWNames option saves a placement
   plot with nodes labelled.
  The -save option saves a placement (out.pl)

*** How to set fixed locations for cells ***

  To set fixed locations for blocks and preserve their
  dimensions, you must provide Capo with input in the
  Bookshelf format rather than in the Parquet format.

  First, convert the floorplanning problem to the Bookshelf
  format by running Capo on it once. Capo will automatically
  save the Bookshelf files:
      {design.aux design.nodes design.nets design.scl design.pl}

  Then, make a node fixed by declaring it as a terminal in
  the design.nodes file, e.g.:
     I75 617 468 terminal

  Now you may run Capo with the Bookshelf files:
        MetaPlacerTest0.exe -f design.aux

*** Region constraints ***

  We are currently adding region constraint support to floorplanning
  in Capo. What you could do in the mean time, is the following:

  - Construct 2 different problems for Capo - one for the top
   half of the circuit, another for the bottom half of the
   circuit, place the NMOS blocks separately from PMOS blocks, and
   combine the 2 placements.

  - If wirelength has to be minimized, one has to add a
   pin-assignment step.  Add a new pin to each cut net, and
   place pins on the cutline (otherwise the two placements
   will be uncorrelated). This can be done either at the
   very beginning or after one of the placements becomes
   available.