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ICCAD04 Mixed-size Placement Benchmarks

Saurabh Adya , Igor Markov , Shubhyant Chaturvedi

Contents

I.  Introduction 
II.  Faraday Benchmarks
III. IBM-MSwPins Benchmarks

IV
Literature


I. Introduction

This entry includes mixed-size placement benchmarks for CAD research. There are 2 suites of benchmarks. The Faraday suite has sufficient routing information to run an industrial router on the placed benchmarks. The IBM-MSwPins benchmarks are an improved version of the original IBM mixed-size placement benchmarks released in ISPD2002. The new IBM-MSwPins benchmarks have non-trivial macro aspect ratios and pin locations for individual cell/macro.

II. Faraday Mixed-size benchmarks with routing information
Faraday Corp. recently released three benchmarks, originally intended for comparisons between structured and conventional ASICs. We apply to these benchmarks a standard ASIC design flow to generate five mixed-size designs. Faraday benchmarks include three commonly-used functional blocks: (I) 16-bit DSP, (II) 32-bit RISC CPU and (III) DMA. Other details on these benchmarks such as the EDA Tools used by Faraday, implementation conditions, settings etc. can be found in on the faraday web-site. To minimize the impact of routing on the results of the accounted placement approaches, we avoid clock-tree generation and power routing in our flows. However, both clock-trees and power rails can be built on theses benchmarks. Following is the description of our ASIC flow which we used for generating the mixed-size benchmarks from the original netlists.

Faraday benchmarks come with the behavioral Verilog descriptions together with timing constraints and relevant scripts needed for synthesis. We use the Artisan's 0.13 micron libraries in IBM Technology for synthesizing these designs under worst-case process conditions, with the same timing constraints as specified in the Faraday design documents. Synopsys Design Compiler (v2003.03-2) was used for synthesis. The embedded memories in these designs were built using the Artisan Memory Generator.  Artisan limits the size of its SRAM memories to a minimum word-length of 128 for dual-port
memories and to 256 for single-port memories. This necessitated the need for a change in the behavioral descriptions of the given designs to account for larger word-lengths. However, Artisan does give an option of building register-files which can be used in place of memories for smaller word-lengths. We explored that option as well and thus came up with two flavors each for DSP and RISC. One that uses only memories and the other which uses both memories (for larger word-lengths) and register-files (for smaller word-lengths).

The gate-level netlists obtained after synthesis are taken through the automatic place and route (APR) flow using Cadence
Silicon Ensemble Ultra (v5.4.126). We follow the Cadence recommended flow for placing mixed-size designs and first use the ``qplace noconfig block'' command to place any macro blocks in the design. After this the macro blocks are considered fixed, the rows below the macros are cut and the remaining standard-cells are placed using the command ``qplace noconfig''. SEUltra also provides an option of concurrent pin placement during the placement process to minimize wirelength. Apart from wirelength reasons, we also exercised this option in our flow to improve routability, which was not being achieved without violations by a random I/O placement at the time of floorplanning.  The routing of Artisan memories together with the standard-cells using a grid-based router like WarpRoute requires certain offsets to be made in the routing grid to avoid geometry violations. These offsets are provided by Artisan itself.  The APR flow consists of the classic steps of floorplanning (creating the layout region) followed by the placement of blocks and standard-cells with QPlace and culminates with routing using WarpRoute. Empirical results for the Faraday benchmarks will be available in ref [1].

Disclaimer: If you are using these benchmarks in a publication or a technical report, please cite the following source [1] in addition to the URL. They describe how the benchmarks were created.

There are 5 benchmarks dma, dsp1, dsp2, risc1 and risc2 available in Bookshelf format and LEF/DEF format.

FARADAY_ICCAD04Bench.tar.gz


III. IBM-MSwPins Benchmarks

These benchmarks have large placeable macros and many fixed pads distributed through the periphery. The benchmarks are derived from the ISPD-98 (IBM) circuit benchmarks. We converted the netlists into the Bookshelf placement format and added placement-related information. The original descriptions specify cell areas, but not their dimensions.  We define rows of height 16. Cell sites in all rows have width 1. Cell widths were computed by dividing cell areas by row height (16). When the width of a cell exceeded a threshold, we upgraded such a cell to the status of a multi-row macro. The aspect ratio of the macro is randomly chosen between 0.5 to 2.0. The pins of all cells/macros are spread around the periphery of the respective cell/macro. The pin locations are determined from an initial placement of benchmarks with all pins located at the center of the respective cell/macro. All designs have a whitespace of 20% and their pads (marked in the original IBM netlists) were randomly placed near the perimeter of the core area. Empirical results for the IBM-MSwPins benchmarks will be available in ref [1].

Disclaimer: If you are using these benchmarks in a publication or a technical report, please cite the following sources [1] and [2] in addition to the URL. They describe how the benchmarks were created.

There are 18 benchmarks, ibm01-ibm18, available in Bookshelf format and LEF/DEF format.

ibmMSWpinsICCAD04Bench_BOOKSHELF.tar.gz (Boofshelf format)

ibmMSWpinsICCAD04Bench_LEFDEF.tar.gz   (LEF/DEF format)


IV. Literature

[1] S. N. Adya, S. Chaturvedi, J. A. Roy, D. Papa, I. L. Markov, "Unification of Partitioning, Floorplanning and Placement", International Conference of Computer Aided Design (ICCAD), San Jose, 2004.

[2] S. N. Adya, I. L. Markov, "Consistent Placement of Macro-Blocks using Floorplanning and Standard-Cell Placement", International Symposium of Physical Design (ISPD), San Diego,2002.

[3] S. N. Adya, I. L. Markov, "Combinatorial Techniques for Mixed-size Placement", to appear in ACM Trans. on Design Automation of Electronic Systems, 2004