==== Agenda for June 18, 2001 =============================================
==== Embassy Salon Suite,  Las Vegas Hilton ===============================

  8:00am-11:00am

  1. Where we want to go   vs   what we have now
     8:00-8:40 
               (only relatively new contributions will be covered in depth,
                   *at most* 5 mins per contribution)
 
       - here are three of many bookshelf objectives
           - to provide relevant benchmarking infrastructure
              for research, publishing and industrial use
           - offer high-qualify tools in source code
           - integrate tools into tool flows
       - at the moment, we are mainly focused on physical design 
       - we have
           - partitioning, floorplanning and placement benchmarks
           - floorplanner in Java (no source?)
           - partitioners (MLPart, hMetis)
           - placers (Capo, Dragon, Feng Shui)
           - a global router (Labyrinth)
           - a DB with LEF/DEF parsers and PERL/Tcl/Python interfaces
           - scan chain
           - RSMT/RMST and BST
           * know-how regarding integration with Cadence and IBM P&R tools
           - links to lots of related general-purpose goodies
              - network-flow solvers
              - LP and non-linear solvers
              - etc, etc...
       - we need
           - feedback from the industry and use by the industry
           - more integration, esp. with commercial tools
           - wider participation and adoption
           - to refine future focus
       - questions and discussion (up to 10 mins)

  2. Industrial participation/requirements and vertical benchmarking
     8:40-9:20 (two talks 10-15 mins each followed by a 10-min discussion)

       - Paul Villarrubia, IBM
         "An overview of important features for industrial placement problems"
          - addresses issues of relevant benchmarks and industrial adoption
       - Herman Schmit, CMU
         "The Vertical Benchmarking Project at CMU"
          - addresses  issues of relevant benchmarks and tool integration
       - questions and discussion (up to 10 mins)
       
  3. Other on-going work 
     9:20-10:15 (*at most* 5 mins per project, 10 mins for Qs/discussions)

       - Roy/Ivan:  optimal clock skew scheduling
       - C.-K. Cheng:  interconnect delay/timing analysis 
       - john lillis:  SITS (p-tree package, in particular)
       - integration and comparisons with commercial tools
          - Cadence Pearl, WarpRoute (UCLA, UMich)
               e.g., CapoT -> Pearl -> WarpRoute -> Pearl
          - IBM ChipBench (UMich, IBM)
               e.g., CapoT -> EinsTimer -> XRouter -> EinsTimer
       - "simple" (but not easy) benchmarks w/o all bells and whistles
          - solvable with both commercial and academic tools
          - can give apples-to-apples comparisons
          - WL-driven and timing-driven placement (UCLA, UMich)
          - routing benchmarks (UMich)
       - new tools
           - an open-source floorplanner in C++ (UMich)
           - more versatile open-source routing tools
             (UMich, SUNY, etc)
           - ucsd is committed to filling in special engines 
                 (clock, power, test, area fill, etc.) 
              that are needed to get reasonably complete
              layouts (without these elements, some flows simply won't
              work, e.g., you can't route a clock tree after routing
              all other signal nets)
       - questions and discussion (up to 15 mins)
 
  4. Current challenges
     10:15-10:30 (emphasis on discussion)

       - "separating" global and detail routing 
         (data format, evaluations, at least one engin for each)
       - "merging" floorplanning and large-scale placement
       - correlating and anti-correlating
          * placement wirelength with routability and routed WL
          * placement wirelength with timing objectvies
       - formulating and validating "simple"/clean design metrics
         and optimization objectives for consistent research
         in multiple groups (e.g., the overflow metric used by
         Majid's group)
       - discussion (up to 10 mins)

  5. Future foci ?
     10:30-11:00

       - more attention to data-modeling ?
       - fully open-source CAD design flows?
       - comprehensiveness
       - formulations of open problem submitted by the industry ?
         (remember the "Top-ten list for Physical Design" at ISPD ?)
       - more formal and automated interface 
          - peer reviews
          - hit statistics
       - lobbying for an official status with DAC ?
       - "same old"
          - more benchmarks ?
          - better tools ?
          - more empirical comparisons ?
       - discussion (up to 15 mins)