CLKISPD05 Register Placement Benchmarks
Contents
I.Introduction
This slot includes register placement benchmarks for CAD research.
II.
CLKISPD05 Benchmarks
These benchmarks are directly derived from industrial ASIC designs, with
circuit sizes ranging from 210K to 2.1M placeable objects. We adapted eight
designs from the ISPD 2005 placement contest benchmarks and created register
lists in which 15% of standard cells are selected to be registers. We selected
the number 15% based on the industrial designs introduced in [2], where the
average 14.65% of cells are registers. The largest benchmark has 327K
registers. Fixed macro blocks are viewed as routing blockages during
clock-network synthesis. The benchmarks are mapped to the Nangate 45 nm open
cell library [3] to facilitate clock-network synthesis with parameters from
ISPD 2010 CNS contest. The standard-cell height (or row height) is set to 1.4
μm according to the 45 nm library.
III.
The
Benchmarks
Disclaimer:
If you are using these benchmarks in a publication or a technical report,
please cite the following sources [1] in addition to the URL. They
describe how the benchmarks were created.
There are 8 benchmarks available in extended
Bookshelf format. Please read README file for more information about
extended Bookshelf format.
CLKISPD05.tgz (Extended Boofshelf format)
IV.
Literature
[1] D.-J. Lee, I. L. Markov, "Obstacle-Aware
Clock-Tree Shaping during Placement", International
Symposium of Physical Design (ISPD), Santa Barbara, 2011.
[2] Y. Cheon, P.-H. Ho, A. B. Kahng, S. Reda and Q. Wang, "Power-Aware
Placement", Design Automation Conference, 2005.
[3] Nangate Inc. Open Cell Library v2009 07, 2009.