==== Agenda for Sept 7, 2001 =============================================
==== Grand Ballroom, Salon E, Santa Clara Marriott =======================

  8am-9am : Breakfast
  9am-9:30am: (joint meeting with the Technology Extrapolation group)
              Status of GTX and bookshelf; Workshop goals
  9:30-9:45   General announcements about new/updates slots and entries
              SITS, delay calculation, Steiner trees, global routing, 
              SAT, vertical benchmarks, floorplanning,...
  9:45-10:15  Updates on individual slots and work in progress
               - the SITS slot, Milos Hrkic (UIC)
               - Performance Optimization by Lagrangian Relaxation 
                 Yu-Min Lee (UWisc.)
               - Optimized Spanning and Steiner Trees, Ion Mandoiu (UCLA)
  10:15-10:45 "Interoperability of Bookshelf P&R Slots with Industrial 
                 Design Environments at Intel", Karthik Rajagopalan (Intel, SC)
  10:45-11:15  Discussion: Group Effort on Interoperability and Interfaces;
                  (review of the needs of FP/P/R/tree-analysis slots 
                   and plans for integration)
  11:15-11:45 ``Executable Extensions of the Bookshelf",
                Marius Eriksen (Univ. of Michigan) 
  11:45-12noon Discussion: Educational Aspects of the Bookshelf.